1. Field
This disclosure relates generally to non-volatile memories (NVMs), and more particularly, integrating NVMs with high voltage transistors.
2. Related Art
The integration of non-volatile memories (NVMs) with high voltage transistors is particularly significant because NVM cells typically use significantly higher voltages for program and erase than the power supply voltage. Most of the transistors generally operate at the power supply voltage and are manufactured with that voltage in mind. The generation and use of the higher voltages required for program and erase require transistors that can operate at those higher voltages. Also, it is common for there to be a need for some ability to handle higher voltages than are used by most of the logic transistors, especially at inputs which can be from higher voltage products such as batteries and even USB inputs. This is often a situation of an analog to digital conversion. The high voltage transistors typically have a thicker gate dielectric than the vast majority of the logic transistors which can create difficulties in manufacturing. The desire is to have a high quality gate dielectric regardless of the thickness. Thermally grown oxides for this purpose are typically the highest quality gate dielectric but it is also desirable to avoid removing a layer on the gate dielectric by etching. Achieving both of these desirable characteristics can be difficult to achieve. Also there is an undesirable effect of having to grow a particularly thick oxide which consumes silicon and thus lowers the top surface of the semiconductor substrate. In etching this and other oxides, there are divots formed at the interface between the isolation regions and the active regions.
Accordingly there is a need to provide a high voltage transistor integration that improves upon one or more of the issues raised above.